One of the areas Intel focused on during its Architecture Day 2020 event was its ongoing work to improve interconnect technology in both 2.5D and stacked 3D chip configurations. We’ve talked about these technologies in the past — they range from EMIB (used for Kaby Lake-G) and Foveros (Lakefield) to upcoming concepts like Intel’s Omni-Directional Interconnect (ODI), which blends the previous two methods.
At the same time that Intel has been talking up its interconnect technology, however, the company has been struggling on the CPU front. Intel first discussed Foveros in late 2018, and in the 18 months since, it’s faced down a major 10nm delay and the recent news about its 7nm product lines. Given the difficulties the company has faced, you’d be forgiven for thinking its sudden interest in interconnect and packaging reflected a need to find a positive topic of conversation.
Intel’s overall packaging roadmap.
In this case, Intel’s focus on how we connect chips together isn’t an attempt to avoid talking about its manufacturing issues. The only thing that makes chiplets an advantageous strategy compared with existing methods of die integration is that manufacturers are deploying new technologies to minimize the power and latency impact of moving various components further apart.
One way chip designers can continue to improve transistor density in the face of weaker process node scaling is by stacking more chips on top of each other. 3D NAND has been on the market for several years, but it took longer to develop a method of stacking logic chips on top of each other that didn’t result in a metaphorical heap of melted wire and scorched silicon as soon as you ran a serious workload through it. Cost, TSV routing issues, and manufacturing integration have all been serious challenges to the adoption of high-end packaging technologies.
For a different example of this trend at work, consider HBM. AMD used High Bandwidth Memory for its Fury family of GPUs just over five years ago. If HBM had followed the adoption trend of previous memory technologies, it would now be ubiquitous across both AMD and Nvidia’s product lines. Instead, HBM has received a follow-up enhancement in the form of HBM2 without ever truly going mainstream and neither AMD nor Nvidia is expected to use HBM2 in their upcoming refreshes. HBM2 still offers a power and performance advantage compared with GDDR6, but it’s expensive and difficult enough to achieve that both firms reserve it for their professional and enterprise GPUs.
As for why companies have pivoted from focusing on transistors to packaging, it’s out of necessity. As the improvements offered by each new process node decline, companies are looking to optimize other aspects of their designs. 3D Chip stacking could allow a CPU designer to minimize internal latency by positioning functional blocks on top of each other, rather than simply putting them side-by-side. Pursuing more cost-effective methods of interconnection and aggregation is how we’ll drive down the cost of mounting memory closer to the CPU and improving overall performance characteristics. The work Intel is talking about on the interconnect front is critical to long-term performance improvements and better power efficiency.
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